I’m not exactly sure what you’re getting at, but I think I’ve had a similar question: why don’t HDLs have language elements more representative of what digital circuits are constructed from, namely synchronous and asynchronous circuits, rather than imperative input triggered blocks (processes IIRC, it’s been a while)?
I always thought it was confusing to design a circuit mentally (or on paper) out of things like muxes, encoders, flip flops, etc. and not have language-level elements to represent these things (without defining your own components obviously).
I remember looking this up, and I believe it’s because the languages were originally designed for simulation and verification, and there are things you might want to do in a simulation/verification language for testing that are outside of what the hardware can do. Mixing the two is confusing IMO, but clearly demarcating the hardware-realizable subset of the language would be better than the current state.
You generally do not want to simulate or describe raw gate-level netlists. Both languages are capable of that. Old school Verilog (not SystemVerilog) is still the defacto netlist exchange format for many tools.
It's just aggravatingly slow to sim and needlessly verbose. Feeding high-level RTL to Verilator to do basic cycle-accurate sim has exceptionally fast iteration speed these days.
Is it really if you restrict yourself to sensible design practices? You generally want to simulate simple clocked Logic with a predefined clock, most of the time anything else is a mistake or bad design. So just if rising edge clk next_state <= fn(previous_state, input) . It seems to me VHDL and verilog are simply at the wrong abstraction level and by that they make simulation needlessly complicated and design easy to do wrong. To me it seems that if they had the concept of clocks instead none of this would be necessary and many bugs avoided (but I'm no expert on simulator design, so I might be missing something...)
I agree basically with everything you're saying, but that's not arguing for raw gate netlists. If anything it's arguing for even higher levels of abstraction where clock domains are implicit semantic contexts.
Many new school HDLs are working in this space and they couldn't be farther from the "representative of what digital circuits are constructed from" idea. Often they're high-level programmatic generators, very far from describing things in terms of actual PDK primitives.
In a way is further away, but in another way it's actually closer to how real hardware works: Clock (and reset) trees are real physical things which exist on all digital chips.
Maybe, another possibility is the frontier providers change their pricing terms to try to capture more of the value once a sufficient number of people’s skills have atrophied. For example: 20% of the revenue of all products built with $AI_SERVICE. For someone several years out of practice they may have no other option.
Insiders bring information to a market. Intelligent analysis and prediction also does, but obviously insiders have special information they are incentivized to bring to the market. Most people placing these bets are simply gambling, insiders and analysts at least have rational reasons for placing bets and add information to the market.
This is a fundamental misunderstanding of why index funds are effective. Being over invested into U.S. equities is a risk if you hold outsized U.S. index funds (esp. if you have a large allocation in the S&P500, you do not own the market portfolio), but there are other risks being invested into foreign equities as a U.S. investor.
“Not listening” is really an incredible framing for trying to flee being detained for obstruction, and in the process hitting and nearly running over a federal agent in your SUV.
Where did I say that? It’s ultimately up to a jury to decide whether lethal force was justified. Obstruct and provoke law enforcement at your own peril.
It’s ultimately up to a jury to decide whether she was trying to flee being detained for obstruction and was in the process hitting and nearly running over a federal agent in her SUV.
This will remain the case until we have another transformer-level leap in ML technology. I don’t expect such an advancement to be openly published when it is discovered.
There is a fan project that has revived the servers. It’s hard to get full matches but can still be played at least. It’s called BLRevive, there’s a Discord for it. IMO the only bad thing is it’s based on the post-PS4 update where the devs console-fied the game.
I.e. disassociating from those people? Isn’t that what homeschooling does inherently? It’s more likely that kids will pick up bad behaviors than they will learn to “deal with” those kinds of people.
Even if the prompts are technically leaked to the provider, how would they be identified as something worth optimizing for out of the millions of other prompts received?
I always thought it was confusing to design a circuit mentally (or on paper) out of things like muxes, encoders, flip flops, etc. and not have language-level elements to represent these things (without defining your own components obviously).
I remember looking this up, and I believe it’s because the languages were originally designed for simulation and verification, and there are things you might want to do in a simulation/verification language for testing that are outside of what the hardware can do. Mixing the two is confusing IMO, but clearly demarcating the hardware-realizable subset of the language would be better than the current state.
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