I'm not sure there are actually any predictions in this article. To sum it up, in the future, transistors will be smaller, more power efficient, they may or may not use differnt materials, and the technology may or may not already exist in the lab.
To be fair, they predict that transistors will be everywhere including places where they (mostly) aren't found today such as in our bodies and close to our food.
The tech isn’t what makes those ridiculous. It’s that there are a million and a half less obvious ways to achieve this goal. Starting with the fact we all carry our phones with us everywhere.
When technologists say that transistors (read: computers) are going to be in literally everything, even in people's bodies, some people find that scary and interpret that as a threat. They ask: why do these things suddenly need computers in them? Bodies have gotten along fine without them for millions of years. Why the sudden change? Conspiracies will emerge to answer that.
It's the "natural == good" fallacy. Humans have lived with problems like disease, aging, and death for millions of years. If technology can help to alleviate or solve these problems then that is a good thing.
Will they actually be smaller, though? AIUI, industry consensus is that future progress will come from 3D-stacking multiple layers of transistors on the same die, not from finer lithography.
It's possible to make single-atom transistors (demonstrated 2004), but I have no idea if there's a planned path to making tens of billions of those at a time, in a single chip, that doesn't cost more than a few hundred USD.
Few years back I came across this term memristor that was supposed to be the next evolution in transistors. Anyone has any idea on this and what's happening in this area?
Perhaps, a moonbase with access to permanently dark low temperature environment will take advantage of superconducting properties couple to quantum field educated guesses.
I can’t answer your question specifically, I’m not up to date on the latest developments. But I do think it’s worth mentioning, generally speaking, that light is harder to deal with than electricity. It requires bigger structures and those structures are inherently lossy. I think the issue has always been related to signal deterioration as the light propagates and the inability to “store” light, like how you can store a charge. This is a fundamental problem with using light and I wouldn’t expect some new engineering effort to overcome it. Speaking as an optical engineer.
There are now commerically available products and lots of companies working in the space. I remember way back when they'd managed to make a ring buffer which seemed like black magic yet here we are now (no idea if the r.b. was implemented the same way now, I lost touch with what was going on)
Does anyone have any info or insight into the current landscape of transistor design and development?
I recall there was a very interesting concept being kicked around a few years ago and I'd love to know what happened to it, but my head is now too full of other technical knowledge that I'm drawing a complete blank.
Some form of monolithic 3D is a must to continue Moore's law. Monolithic 3D is different from stacked dies because you make layers of transistors on top of other transistors, instead making them separately, and gluing them together later.
CMOS will transform into something where PMOS, and NMOS part will be combined into one. IMEC already has working forksheet CMOS where P an N parts are sitting side by side. Ideally, N, and P parts will be stacked on top of each other.
All around gates will likely be adopted, either vertical, or horizontal, as they seem to be even easier to do than fins for a given level of performance.
Power will be put onto other side of the die, or buried under epi layer — already in works, and seem to be working well. TSVs will get small enough to use vias to connect individual transistors. Metal routing is getting increasingly more permissive with EUV in general.
New middle-end metals — a possibility.
COAG — already working on latest FinFETs. The metal contact is descended directly onto the gate, rather than on a space near it. All barrier layers are grown directly on top of it as well.
Individual cells will get verticalised as well, and most device development will be done with cells being treated as one device.
We may find a way to put a layer of 3-5 semiconductor on top of silicon wafer to use it for either P or N part of a CMOS device.
Fundamentally new types of FETs are dark horses, and it may well be we may go away from FETs for most high performance comping chips. For always working devices, the relative power efficiency difference of BJT is getting better, and better as device size gets lower. TFETs, and other subthreshold devices can also turn mainstream very fast if people will find ways to work around their inherent issues.
Talk about covering all potential bases.