Sandy Bridge was the last CPU uArch changes that we got 20% IPC increase. Since then everything has been ~10% spread up with majority leaning towards floating point with new instructions.
I often spend time wondering the transistor count difference between modern Efficiency Core and Sandy Bridge. If you compare the two [1], SandyBridge vs Gracemont. It is clear the difference where Gracemont Support for AVX, AVX2, FMA3 and AVX-VNNI instructions makes.
The SandyBridge was fabbed on 32nm, Gracemont on Intel 7, would a modern SandyBridge on Intel 7 have similar die size as Gracemont? Or they could have sold me a SandyBridge on Intel 7 on a Raspberry Pi like devices.
I often spend time wondering the transistor count difference between modern Efficiency Core and Sandy Bridge. If you compare the two [1], SandyBridge vs Gracemont. It is clear the difference where Gracemont Support for AVX, AVX2, FMA3 and AVX-VNNI instructions makes.
The SandyBridge was fabbed on 32nm, Gracemont on Intel 7, would a modern SandyBridge on Intel 7 have similar die size as Gracemont? Or they could have sold me a SandyBridge on Intel 7 on a Raspberry Pi like devices.
[1]https://browser.geekbench.com/v6/cpu/compare/2135149?baselin...