It's true that you require a very rare and profound skill set to develop those tools (i.e. experts in software as well as chip design) but it's not as complicated as you describe. Scaling is trivial when you've got your data architecture right (because chip designs and layouts scale like maps basically) and there are zillions of low hanging fruits to harvest because any halfway modern UI or tool flow will easily outperform the interface mess that the commercial tools are offering you. People who are using open source EDA tools for automated/ai-assisted chip designs are already demonstrating this in publications this btw. Moreover, there is more than advanced node VLSI. You have analog, custom digital, RF, cryo, etc., etc., where better automation, more flexibility in workflow and interfaces, and dramatically reduced costs for tool access could actually revolutionize the entire field on a very small time scale.