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Sadly that display controller MISO thing is notorious. I first ran into it a few years ago. The recommendation was to use a tristate buffer on the chip select line or, as you did, separate the buses.

I also run into the power domain issue a lot. I didn't see a graphic about it in the article but essentially in the majority of devices the IO is like this:

Vdd

|

Esd diode

|

I/O pin

|

Esd diode

|

Ground

Where the diodes are pointing towards. That way if the line goes too negative the lower one will conduct and clamp it to a diode drop + ground, same as if it goes too high to a diode drop + Vdd. The problem is if Vdd has a low impedance path to ground. This is common with power supply ICs either with output discharge resistors or transistors allowing current through to ground. When that happens, your io pin now has a diode in parallel to ground. If you're not careful and don't have current limiting resistors in the way I2C does (because it needs the pull ups), suddenly you're putting the max current your driver can deliver through that diode. Doesn't take much for the smoke to escape.

Some IO pins are designed to be fine without VDD. You can usually check the absolute max ratings for someone like "VDD + 0.3" vs "3.6"



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